1. Field of the Invention
The present invention relates to power regulators, and more particularly to adaptive PWM pulse positioning for fast transient response by reducing the blank period between cycles.
2. Description of the Related Art
The load current of modern circuits including the modern central processing unit (CPU) is highly dynamic and changes very quickly from low to high and from high to low. A CPU current transient may occur within 1 microsecond (μs), for example, which is less than the typical switching period of conventional voltage regulators. It is desired to provide a DC-DC power regulator with a control loop that has sufficient response time to fast load transitions whenever they occur.
In many conventional pulse-width modulation (PWM) schemes, the compensation output of an error amplifier is typically compared to a fixed ramp signal by a PWM comparator. The PWM comparator generates a PWM signal used to control switching of a DC-DC power regulator. To provide switching noise immunity, a reset-set (R-S) flip-flop is often coupled to the output of the comparator to ensure that there is only one pulse for each switching cycle. In a leading-edge modulation scheme, each PWM pulse is initiated based on the comparator output and terminated synchronous with a clock signal. The leading-edge modulation scheme is good for the load-adding transient event but not always responsive to a load-releasing transient. In a trailing-edge modulation scheme, each PWM pulse is initiated synchronous with a clock signal and terminated based on the comparator output. The trailing-edge modulation scheme is good for the load-releasing transient event but not always responsive to a load-adding transient event. In a conventional dual-edge modulation scheme, the ramp is a triangular waveform so that each PWM pulse begins and ends based on a comparison of the triangular waveform with the compensation signal. The conventional dual-edge modulation scheme, however, also exhibits turn-on or turn-off delays since the ramp is fixed and since the leading-edge of the PWM pulse occurs only in the first half cycle while the trailing-edge only occurs in the second half cycle. Each of these conventional schemes, therefore, insert clock signal delays under certain load varying situations.